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matrixofdynamism
Xilinx MPSoC and RFSoC, what is the big deal?
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on: July 25, , 11:10:26 am »
Xilinx invented the Zynq device which combined an ARM core with programmable logic. This was more than 15 years ago I believe.
More recently they released MPSoC and RFSoC FPGAs. From what I know these are massive FPGAs and contained multi-core ARM processors. Now the question in my mind is, what is the big deal? What makes these MPSoC and RFSoC devices special or distinct? We have had ARM core with programmable logic for more than a decade in the market and from different suppliers as well.
Herby
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #1 on: July 25, , 11:23:52 am »
As far as I can tell, you've answered your own question already. They're more modern versions of the Zynq. They're bigger, faster and more expensive, but there's nothing fundamentally new.
Small incremental improvements is all you get with mature products (with very rare exceptions). That's true for processors, mobile phones, airplanes, ...
ejeffrey
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #2 on: July 25, , 03:18:53 pm »
The big deal with the RFSoC was including a ton of high speed data converters on the same chip. This makes it extremely attractive for custom data acquisition devices, high performance SDR, and similar applications.
The MPSoC is basically just a bigger zynq. It has a multi core 64 bit arm CPU, and it also has a dedicated cortex-R processor for realtime and fault tolerant applications. But the people I know who use them don't really care about those features, the main thing is the much bigger and higher performance programmable logic with many more and faster high speed transceivers. For instance some versions of the MPSoC can support 4 100 gigabit Ethernet ports. It's also got more bram, UltraRAM (high density psuedo dual port memory) and more DSP resources.
glenenglish
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #3 on: July 25, , 09:23:49 pm »
Ultrascale+ parts like MPSoC are revolutionary, compared to 7 series Zynq.
With Ultrascale+, you can utilize, (depending on the design) right up to 99% before they slow down. Compare to 7 series that slow down at > ~ 70% (design dependent). They are awesome.
and the fabric is fast --even in the slowest parts, 650 MHz+ multipliers....
The dual core R5 can run lockstep and is in its own power domain. The R5 is not just another ARM cortex M, it is a processor that can unwind itself out of trouble, out of aborts, sorts out instructions half executed etc, it is design to keep on trucking
With all this comes a great deal of complexity. beware of this ! You could learn every about MPSoC and it might take you a lifetime.
You can spend a year reading the datasheets thoroughly. And, you want a simple watchdog ? then you better get to know and write custom firmware for the PMU !
But Altera 10nm Agilex 5 with HPS ( in midrange 50k-300k) will go head to head and beyond later this year in production.... Unless you need to go to market now, I think Agilex5 is worth waiting for.
RFSoC is fantastic, but IMO is only useful when you need half a dozen 5GHz converters, and their dynamic performance is not particularly good at < 500 MHz compared to say, a $35 12 bit 250 MHz converter, but they are not designed to compete in that region. they compete in the 1-10 GHz large instantaneous BW region.
7 series ZYNQ still holds the market sweetspot below then 50k LE region though, and small 225 and 400 0.8mm ball packages
Other notable SoC options are Microchip Polarfire SoC , Efinix Titanium SoC, . Forget Cyclone IV SOC.. ROFL.
« Last Edit: July 25, , 09:31:32 pm by glenenglish »
matrixofdynamism
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #4 on: July 26, , 09:35:25 am »
Could someone give example of what Ultrascale+ MPSoC would be used for? The MPSoC and RFSoC seems to be rather niche with those powerful data converters and different type of ARM processors.
So the MPSoC contains an M processor and an R processor. Why would anyone need so much power in programmable logic device? I have heard before that these devices are so complex that it would take a whole lifetime to learn them fully. I am still not sure of why this is the case.
asmi
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #5 on: July 26, , 02:49:44 pm »
Could someone give example of what Ultrascale+ MPSoC would be used for? The MPSoC and RFSoC seems to be rather niche with those powerful data converters and different type of ARM processors.
So the MPSoC contains an M processor and an R processor. Why would anyone need so much power in programmable logic device? I have heard before that these devices are so complex that it would take a whole lifetime to learn them fully. I am still not sure of why this is the case.
Easy - PL is to perform the primary function of a device, and PS is to run the HMI (GUI, peripherals, etc.). A lot of devices require APU to run the HMI in addition to the main FPGA which does the processing. Combining these into the single chip has a lot of advantages - smaller PCBs, less power consumption, easier routing, etc. If only these MPSoCs wouldn't cost so much, they would be a no-brainer for a lot of applications.
My blog - All things electronic
DIY Spartan-7 FPGA board for beginners: https://www.eevblog.com/forum/fpga/custom-spartan-7-board-for-beginners/
KE5FX
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #6 on: July 26, , 08:06:03 pm »
You tend to see the SoCs used in MIMO applications like cellular base station transceivers, or in high-end radar work where cost is no object. For everything else, it is usually going to be cheaper to hook your own choice of ADCs and DACs up to your own choice of FPGA and controller hardware.
At least that's been the case historically.
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radar_macgyver
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #7 on: July 27, , 02:13:11 am »
RFSoC's big advantage relative to a big FPGA coupled to high speed converters is that the interface between the two (in the latter case) is non-trivial. Even with standardization like JESD204B, it's really hard to get right even when using someone else's known working boards. Integrating the converters on chip means you have direct access to the parallel data stream without a complex SERDES in between. The drawback is that the converters can have noise coupling in from the digital part of the SoC. They are also really expensive.
ejeffrey
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #8 on: July 27, , 04:47:31 pm »
An RFSoC in volume direct from Xilinx is actually competitive with stand alone FPGA + high speed data converters. And for low volumes, the eval boards are not exactly cheap (~$15k), but are a real bargain considering what you get and what it would cost to get an equivalent.
In addition, the interconnect bandwidth is higher. Even with JESD204b/c, high speed DACs are generally bandwidth starved and they use internal digital interpolation and upconversion to get the high sample rate, but the instantaneous bandwidth is limited. Or you can disable some channels in multi-channel device to devote more digital bandwidth to a single channel, but that increases your cost a lot.
Of course in addition to possible noise, a limitation of the RFSoC is that you only get the configurations xilinx makes. If it's overkill for your needs you don't get a discount, while if it's not sufficient it won't work.
radar_macgyver
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #9 on: July 27, , 05:27:09 pm »
An additional concern with JESD204 is that if you change the sample rate (or interpolation/decimation config for converters that support it), one must go through a lengthy retraining and re-syncing sequence. With the older (external) parallel converters, this was not usually a concern. I haven't worked with an RFSOC yet (too expensive!) but I imagine it will be similar in this regard.
To be fair, most applications such as cell base-stations or radar transceivers don't require frequent sample rate changes. Oscilloscope digitizers would need this ability, though.
In addition, the interconnect bandwidth is higher. Even with JESD204b/c, high speed DACs are generally bandwidth starved and they use internal digital interpolation and upconversion to get the high sample rate, but the instantaneous bandwidth is limited. Or you can disable some channels in multi-channel device to devote more digital bandwidth to a single channel, but that increases your cost a lot.
There are some rather impressive parts like the ADC08DJRF that can do 10.4 GSPS without internal decimation, but require eight JESD204 lanes at 17 Gbps for a single channel. The newer RFSOCs now include hard-IP digital downconverters. Most communications/radio applications for such devices would use a DUC/DDC anyway so it's not much of a loss.
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glenenglish
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #10 on: July 27, , 09:25:25 pm »
I have worked with RFSoC parts. Fantastic for specific jobs. If you are worried about cost, then you are trying to use it in the wrong market.
IMO, they're only cost effective compared to multiple 5Gsps converters, and the spurs in the passb relegate it to wideband functions, as the SFDR isnt really all that great for any high dynamic range narrowband application, and the sampling clocks are polluted.
There's another aspect for their use - and that is link power consumption
as radar_macgyver says, high speed external DCs , they chew up JESD lanes like nothing else. That has a power cost and silicon area cost to get between the DC and the FPGA. extra pain avoided by one package.
For the ADC side - If used as a back end , with a bandpassed and gain controlled front end (to limit the required dynamic range from the converter) they are a good option.
The huge signal processing capability on board is I think driven my wideband radar applications (wideband, lots if computation) and cellular base stations. Both are relatively low dynamic range applications.
When the fabric multipliers run at 650 MHz and you are filtering a signal (say a wideband correlator ) at 5 Gsps, you chew up multipliers and rams big time.... A 100 tap non symmetrical fir is going to chew multipliers ! LOL.
« Last Edit: July 27, , 09:29:36 pm by glenenglish »
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radar_macgyver
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #11 on: July 28, , 01:15:35 am »
For the ADC side - If used as a back end , with a bandpassed and gain controlled front end (to limit the required dynamic range from the converter) they are a good option.
The huge signal processing capability on board is I think driven my wideband radar applications (wideband, lots if computation) and cellular base stations. Both are relatively low dynamic range applications.
(emphasis mine)
Spot on - my usual radar applications are the opposite (relatively narrow-band, very high dynamic range). I'm curious what the applications of wideband radar are, if you're allowed to share (the only one that comes to mind is ground-penetrating radar). For narrowband (or indeed, multiple narrowband channels, typical of basestation applications), an off-chip converter with integrated DDCs would be significantly lower cost. Power consumption increase due to the JESD204 lanes and their associated transceivers will likely be offset by the thousands of DSP blocks!
matrixofdynamism
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #12 on: August 01, , 01:17:59 pm »
FPGAs are themself not ubiquitous like ARM based cores or other microprocessor, microcontroller and DSPs. However, it seems that even within the FPGA domain, the RFSoC and MPSoC are for niche applications. The demand must be high enough that Xilinx went ahead and created such devices.
What I have understood is that the integrated data converters are a huge plus. But what about the multicore ARM processors of different types that exist? How would I harness them?
Also, I believe that some other companies (Maybe Microchip) have come with this idea to have a small amount of programmable logic in their microcontrollers. Has anyone used these type of tools at all?
DutchGert
Re: Xilinx MPSoC and RFSoC, what is the big deal?
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Reply #13 on: November 17, , 04:06:12 pm »
These parts are perfect and very impressive if you can use them for our specific use case.
Back in I did a project with the original Zync for a, relatively basic, camera - monitor system in automotive.
It has MIPI in and outputs so you can interface camera and display SerDes devices.
Then, you use the FPGA part for all the parallel image processing and the ARM cores for drawing up a GUI etc.
Few years later, we used the MPSoC for the second generation of this product.
So, we had a big ECU with 6 camera inputs, 3, display outputs, it would do basic object detection (is there someone in the dead corner of my truck, am i still following the road lines etc), do both the video processing, GUI, object detection and vehicle communication with one single chip and, best of all, all of this functional safe and some parts in lockstep.
These parts are really nice. And guess what, they might be on Digikey for USD a pop but we paid around 20 bucks each for them in (big) volume.
Hello, I am using the RFSoC 4x2 with PYNQ, and I’m having some trouble generating some of the waveforms which I want to. Using the loopback method shown in the tutorial RFDC notebook, I want to get started with generating a simple pulse – however, I’m not sure how to transmit a variable waveform. All of the example notebooks used a fixed waveform, where the frequency of the transmission was set before the receiver was set up. However, for something like a pulsed or frequency modulated wave, I will need to have this transmitter waveform change while the receiver is enabled. Can anyone point me in the right direction? Thanks, any help is appreciated.
Hi ak123,
Welcome to the forums!
It sounds like you want to create a signal generator that responds (in some way) to a signal received by the RF ADC. Does this sound correct?
I am interested in this too. In particular, I would like to create a generalised framework for others (such as yourself) to generate their custom waveforms based on feedback from the RF ADC.
Could I ask a few questions?
- What application do you have in mind? Are you focusing on wireless communications, instrumentation, quantum, or something else?
- What kind of signals do you want to generate from the RF DAC? Do you have any equations or algorithms that mathematically describe these signals, or are they reasonably arbitrary?
- What analysis would you like to perform on a waveform received from the RF ADC? How does this interact with the signal generation part of your system?
- Do you have a transfer function, or similar, which describes what you want to achieve?
To answer your question, I am unaware of anything out of the box that will do what you are describing. You will need to design a custom FPGA architecture that can respond correctly to received waveforms (from the RF ADC) and feedback information to the signal generation stage (to the RF DAC).
I’d like to explore this problem further, and the questions above would help me a lot here and hopefully give you back something useful in the future,
Thanks,
David.
Hi David,
Sorry for the confusion regarding the “loopback method”, I don’t think that’s quite what I meant. I did not mean to imply having a system where the DAC transmitter depends on the ADC receiver.
Although that does sound like an interesting problem, I am not quite there yet – I just want to be able to generate different types of waveforms from the DAC, independent of the ADC. For simplicity’s sake, I would just want to be able to connect the ADC to the DAC directly with a SMA connector for now (rather than using separate transmitter/receiver antennas).
From what I understand, in the example notebooks, we are just generating continuous wave waveforms from the DAC – however, I want to be able to generate other types of signals from the DAC, such as pulse waves and frequency modulated continuous waves. Due to the sequential nature of Python, I am not sure how to have a transmitter signal that changes, while the receiver is receiving. Perhaps I have to use multithreading/multiprocessing, but I’m not sure if that is overcomplicating it, or maybe it is simpler to design from the FPGA architecture.
Thanks
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Hi @ak123,
No problem, and I think I can answer your question and offer some advice.
Python does execute commands sequentially due to the Global Interpreter Lock (GIL). However, you can use the FPGA portion of the RFSoC to perform concurrent processing for the transmitter and receiver. Additionally, as I mentioned before, there isn’t any out-of-the-box infrastructure to help you generate arbitrary signals, so you will need to design your own FPGA architecture design, which can be a little tricky if you are new to this. Here are a few tools to get you started:
- MathWorks HDL Coder
- AMD’s Model Composer (which runs in Simulink)
- AMD’s Vivado HLS
- You can also design FPGA architectures using VHDL, Verilog, and other hardware description languages.
It sounds like you want a transmitter and receiver operating simultaneously, which is possible using the FPGA logic fabric. However, to help you progress, my advice is to focus on just one part of the system at the moment and try to list, using bullet points, precisely what you would like to achieve. Then, try sketching out a diagram based on your specification. From here, you can start designing the system components using the tools I have given above for FPGA implementation. It would be best if you have a good understanding of digital electronics to proceed here.
You can see some design examples that the StrathSDR team have implemented below:
- RFSoC-QPSK
- RFSoC-Radio
- RFSoC-OFDM
And, of course, you have the base overlay for the RFSoC4x2, which will show you how to interact with the RF Data Converters on this platform.
Hopefully, this is useful,
Thanks,
David.
Hi David,
Thanks, this was very helpful!
What would designing my own FPGA architecture constitute? With an FPGA design, I would be directly coding the PL, so I would no longer need an overlay from what I understand. Or would I still need to interface PYNQ with the HDL?
Are there any sample HDL (VHDL or Verilog) tutorials for the RFSoC4x2 that you can point me to?
Also, can you please point me in the right direction regarding loading in a new overlay (which files are necessary – tcl, bit, hwh – and where do I upload them?
I am new to the RFSoC4x2/PYNQ framework so I am still trying to understand how everything works.
Thanks for all the help.
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